The Joint Test Action Group (JTAG) developed a 5 pin test access port standard which is commonly referred to as JTAG. JTAG is used for a variety of Integrated Circuit (IC) and board level tests. During IC test and debug it can be helpful to allow the JTAG (TCK) clock to be driven onto the main clock tree. This allows input test vectors to be loaded while the clock is stable and then allows the IC to function under normal operating conditions.
Referring to FIG. 3, in U.S. Pat. No. 9,024,661 to Rooks the prior art developed a method to switch between a system clock and the JTAG clock without glitches. This technique prevents erratic behavior during IC testing, but as designed, is limited to systems where the JTAG and other clocks are synchronous. In many IC's, the JTAG TCK and other clocks of interest are not synchronous and are provided from an independent source. For these systems, the prior art cannot prevent unwanted clock glitches during test, and can result in incorrect failure behavior.
Referring to FIG. 2, a prior art synchronizing circuit uses one or more D flip-flops in series, with the clock inputs being driven from the destination clock domain. When the input is driven, the synchronizer allows time for the output to settle into a known state. The number of flip-flops required is a function of the clock period and settling time for a particular technology.
Referring to FIG. 1, a prior art clock gater combines an AND gate and an active low latch (passes data when clock is low) to ensure that inputs arriving at unknown times do not impact the output clock waveform. This prevents short pulses from entering the system. The input enable to the clock gater must be synchronous with the clock to guarantee that the output does not enter an unknown state.
The prior art has driven control from JTAG (TCK) directly into the enable (gate) input of a clock gater (see FIG. 3) whose clock input is not of the same clock domain. The concern with this design is that asynchronous clocks cannot be timed relative to each other since their phase at some given time will be unknown. This can result in a failure of the clock multiplexing circuitry.